Digital control of low-power switch-mode power supplies (SMPS) can result in significant improvements of the characteristics of power supply system used in applications such as communication systems, consumer electronics, portable devices, and computers. The advantages of digital control include flexibility, low sensitivity on external influences and realization with a small number of external passive components.
Digital implementation also simplifies implementation of power supplies. Analog controllers usually require time-consuming redesign every time characteristics of the supplied devices change, which in modern electronics happens often. On the other hand, modern tools for automatic digital design allow short development process and fast modification of existing designs to accommodate new requirements.
Although the advantages of the digital realizations are known, in low-power applications, analog pulse width modulator (PWM) controllers are mainly used.
One of the main reasons for the sporadic use of digital controllers is lack of low-power hardware solutions for digital-pulse width modulators (DPWM), the key parts of every pulse-width modulated controller. The DPWM is required to operate at high switching frequency, which in existing switching converters exceeds 1 MHz, and to have high resolution (8 to 11 bits). The high resolution is necessary for tight output voltage regulation and for elimination of undesirable limit-cycle oscillations of the output voltage and inductor current.
In existing DPWM solutions the power consumption is usually proportional to the product of switching frequency and resolution and, in some cases, exceeds the power consumed by the output load, resulting in poor overall efficiency of digitally controlled SMPS.
Recent publications demonstrate digital systems that are able to produce high-resolution pulse-width modulated signals at high switching frequencies that range 400 kHz and 2 MHz.
Those solutions also show that the design of a high-resolution high-frequency DPWM is a challenging task. The presented architectures make various design compromises between on-chip area and power consumption, or between switching frequency and the resolution of the DPWM.
Conventional designs using a counter usually require a clock signal at a frequency that is at least several hundred times higher than the switching frequency of SMPS. Hence, they exhibit high power dissipation and require complex implementation when both high frequency and high resolution are required.
Designs that include a ring oscillator (delay cells) and a multiplexer have substantially lower power consumption but generally require a large on-chip area for the creation of high-resolution pulse-width modulated signals. In addition, the switching frequency of these solutions varies due to the variations of propagation times of delay cells comprising the ring oscillator. As a result, switching noise at an unpredictable frequency can occur and influence the operation of supplied devices.
Recently presented hybrid architectures successfully combine the two previously mentioned concepts to decrease the size and power consumption of digital pulse-width modulators. However, these solutions still suffer from the unstable switching frequency.
To stabilize the frequency the use of a phased-lock loop (PLL) and delay-locked loop (DLL) have been proposed in the past. In both of these solutions analog blocks are used to synchronize the frequency of the DPWM with an external clock. Similar to other systems utilizing PLL or DLL structures, the presented DPWM architectures have limited range of locking frequencies and suffer from potential instability problems. In addition, the DLL based realization requires clock frequency, which is only 8 times smaller than that of conventional counter-based solution and hence still has relatively high power consumption. For example, when 1 MHz switching frequency and 10-bit resolution are required the DLL structure requires 128 MHz clock signal. Even more, in the presented DLL based solution the resolution of the DPWM decreases as the switching frequency increases.
Segmented delay-line based DPWM architecture utilizes only two multiplexers and two sets of delay lines (slow and fast) to achieve small area, very low power consumption, and operation at constant switching frequency. In this solutions the propagation times of delay cells in slow and fast delay lines are different and set to have ratio 16:1. A clock propagating through combination of fast and delay cells creates the pulse-width modulated signal. In this solution ideal matching between the delays of the cells is assumed. Since, in reality, this condition is hard to achieve due to imperfections in implementation technology, a mismatch in delay cells usually exists. As a consequence the input-to-output characteristic of the DPWM is nonlinear and in some cases non-monotonic. The non-monotonic characteristic can cause instability of the whole controller and undesirable oscillations at the output of SMPS. In addition, the presented solution is designed for operation at a single switching frequency, as the clock frequency increases the resolution of DPWM decreases. On the other hand, a decrease in switching frequency limits the maximum value of duty ratio to a number smaller than one.